Gate array circuit for decoding circuits

ABSTRACT

A decoder circuit for decoding different combinations of supplied original input address bits, comprising at least one predecode circuit responsive to the original input address bits for producing predecoded signal bits from the input address bits, and a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input address bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input address bits.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and, more particularly, to a decoder circuit for use in a semiconductor memory device such as a read-only memory (ROM) or a random-access memory (RAM) which per se is well known in the art.

BACKGROUND OF THE INVENTION

A certain type of address decoder circuit for use in a semiconductor memory device such as a ROM or RAM device consists of decoder units of a number less than the number of the possible combinations of the bits forming an address signal to be supplied to the decoder circuit. A typical example of such a decoder circuit is the one used for a ROM device which is incorporated in a microprocessor to store microprogramming codes therein. Such a decoder circuit is directly responsive to the original input address signals so that, where each of the original input address signal consists of six bits, a maximum of 2⁶ =64 different combinations or sequences of bits could be used in the decoder circuit. In comparison with such a large number of possible decoder outputs, the decoder circuit actually has a far smaller number of outputs such as, for example, only twelve outputs and, for this reason, requires the provision of a disproportionately large number of active devices or transistors. Such a large number of active devices used in the decoder circuit inevitably results in correspondingly large amounts of capacitances provided by the diffusion regions of the individual active devices and accordingly in reduction in the switching speed achievable of the decoder circuit.

An address decoder circuit of the described type thus sometimes uses a predecode scheme for the purpose of reducing the number of the transistors to be used in the decoder circuit and thereby increasing the switching speed achievable of the circuit. The decoder circuit to implement such a scheme comprises a suitable number of 2-bit predecode circuits which are directly responsive to the original input signal bits. Each of the 2-bit predecode circuits is operative to predecode neighboring two of the original input address bits by producing a total of four different logic ANDs of the two bits and the inverted versions of the two bits. The predecoded signal bits thus produced by the 2-bit predecode circuits are used in some of the decoder units so that only one of the two original input address bits which have resulted in each of the predecoded signal bits is effective in the particular decoder unit with the other of the two bits virtually neglected from use. The result is accordingly that there exits address bits which are not used in the decoder circuit. Such a scheme of the decoder circuit inevitably results in irregularities in the geometrical topology of the decoder circuit fabricated on a semiconductor chip.

It is, thus, an important object of the present invention to provide an improved decoder circuit which is composed of a minimized number of active devices to achieve an increased switching speed of the decoder circuit.

It is another important object of the present invention to provide an improved predecode decoder circuit which effectively uses the original input address bits supplied to the decoder circuit.

SUMMARY OF THE INVENTION

In accordance with one outstanding aspect of the present invention, there is provided a decoder circuit for decoding different combinations of supplied original input signal bits, comprising (a) at least one predecode circuit responsive to the original input signal bits for producing predecoded signal bits from the input signal bits, and (b) a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input signal bits, characterized in that the decoder units comprises a decoder unit responsive to the combination of at least one of the predecoded signal bits and at least one of the original input signal bits.

In accordance with another outstanding aspect of the present invention, there is provided a decoder circuit for decoding different combinations of supplied original input signal bits, comprising (a) at least one predecode circuit responsive to the original input signal bits for producing predecoded signal bits from the input signal bits, and (b) a plurality of decoder units including at least one decoder unit responsive to at least two different combinations of the original input signal bits, wherein the decoder units comprises a decoder unit responsive to selected ones of the predecoded signal bits alone and a decoder unit responsive to at least one of the predecoded signal bits and at least one of the original input signal bits.

In accordance with still another outstanding aspect of the present invention, there is provided a semiconductor decoder circuit including a plurality of decoder units for decoding different combinations of supplied original input signal bits, comprising (a) a first set of signal lines formed on a semiconductor structure, the first set of signal lines comprising a first group of signal lines connected to a source of a first predetermined voltage and a second group of signal lines connected to a source of a second predetermined voltage, (b) a second set of signal lines formed on a semiconductor structure and extending substantially at right angles to the first set of signal lines, the second set of signal lines comprising a third group of signal lines respectively responsive to predecoded signal bits predecoded from selected ones of the original input signal bits and a fourth group of signal lines respectively responsive to selected ones of the original input signal bits (c) a first set of field-effect transistors selectively connected in series to the source of the first predetermined voltage along each of the signal lines of the first group, each of the first set of field-effect transistors being of one channel conductivity type, and (d) a second set of field-effect transistors selectively connected in parallel to the source of the second predetermined voltage along each of the signal lines of the second group, each of the second set of field-effect transistors being of the channel conductivity type opposite to the one channel conductivity type, each of the second set of field-effect transistors having their gates selectively connected to the signal lines of the third and fourth groups, (e) the first set of field-effect transistors arranged along each of the signal lines of the first group and the second set of field-effect transistors arranged along each of the signal lines of the second group implementing each of the decoder units.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawbacks of a prior-art address decoder circuit and the features and advantages of a decoder circuit according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram showing a typical known example of an address decoder circuit used for a ROM device storing microprogramming codes in a microprocessor;

FIGS. 2A and 2B are address maps depicting the schedules in accordance with which the decoder units of the decoder circuit shown in FIG. 1 are to produce output signal bits in response to the original address bits input to the decoder circuit, FIG. 2A showing such schedules in non-matrix form and FIG. 2B showing similar schedules in matrix form;

FIG. 3 is a circuit diagram showing a preferred example of an address decoder circuit which implements a two-bit predecode scheme;

FIG. 4 is a schematic diagram showing the logical configuration of a preferred embodiment of a decoder circuit according to the present invention; and

FIG. 5 is a circuit diagram showing a preferred example of the circuit arrangement implementing the logical configuration of the embodiment illustrated in FIG. 4.

DESCRIPTION OF THE PRIOR ART

As has been noted at the outset of the description, a certain type of address decoder circuit for use in a semiconductor memory device consists of decoder units of a number less than the number of the possible combinations of the bits forming an address signal to be supplied to the decoder circuit. FIG. 1 of the drawings shows a typical example of such a decoder circuit. The decoder circuit herein shown is used for a ROM device incorporated in a microprocessor for storing microprogramming codes therein and is by way of example assumed to be designed for use with a 12-word ROM device (not shown). The decoder circuit is made up of a number of n-channel field-effect transistors respectively denoted by N₀₁ to N₂₇ and p-channel field-effect transistors respectively denoted by P₀₁ to P₂₇. These n-channel and p-channel N₀₁ to N₂₇ and P₀₁ to P₂₇ are arranged to form twelve decoder units D₀, D₁, D₂, . . . D₁₁ each including a plurality of full CMCS (complementary metal-oxide-semiconductor) inverters implemented by the field-effect transistors N₀₁ to N₂₇ and P₀₁ to P₂₇. The decoder units D₀, D₁, D₂, . . . D₁₁ further include logic inverters I₀ to I₁₁, respectively, which provide output address bits of the individual decoder units D₀ to D₁₁, respectively. The decoder units D₀ to D₁₁ are responsive directly to original, viz., supplied address signals through a total of twelve signal input lines which consist of six lines respectively responsive to supplied address bits A₀ to A₅ and six lines respectively responsive to the inverted versions A₀ to A₅ of the supplied address bits A₀ to A₅. Each of the decoder units D₀ to D₁₁ consists of n-channel MOS field-effect transistors connected in series between ground and each of the logic inverters I₀ to I₁₁ and p-channel MOS field-effect transistors connected in parallel between a source of a supply voltage V_(CC) and each of the inverters I.sub. 0 to I₁₁ as shown. The logic inverters I₀ to I₁₁ of the decoder units D₀ to D₁₁ are respectively connected to the word lines of the memory cell array (not shown).

The n-channel field-effect transistors N₀₁ to N₂₇ and p-channel field-effect transistors P₀₁ to P₂₇ forming the decoder circuit are arranged so that the individual decoder units D₀ to D₁₁ of the decoder circuit are operative to produce output address bits O₁ to O₁₁ in response to the supplied address bits A₀ to A₅ and A₀ to A₅ in accordance with the schedules represented by an address map depicted in non-matrix form in FIG. 2A and in matrix form in FIG. 2B. The sign "X" in the non-matrix address map shown in FIG. 2A indicates an indeterminate or variable bit which may be of either logic "0" or "1" value. In the matrix address map shown in FIG. 2B, the axis of abscissa represents binary digits 000, 001, 011, . . . 111 (increasing from left to right) coded by the lower three of the six supplied address bits A₀, A₁, A₂, . . . A₅ while the axis of ordinate represents binary digits (000, 001, 011, . . . 111 (increasing downwardly) coded by the upper three of the address bits A₀ to A₅. As will be seen from these address maps, each of the decoder units D₂ and D₇ of the address decoder circuit is operable for selecting one of two different sequences of address bits 000010 and 000011 (D₂) or 100100 and 100101 (D₇). On the other hand, each of the decoder units D₃ and D₆ is operable for selecting any one of four different sequences of address bits 000000, 00001, 000010 and 000011 (D₃) or 100000, 100001, 100010, 1000011 (D₆). Furthermore, each of the decoder units D₄, D₅, D₁₁ and D₁₂ is operable for selecting any one of a total of eight different sequences of address bits.

When an original input signal A₀ A₁ A₂ A₃ A₄ A₅ in the form of, for example 00001X is supplied to the decoder circuit shown in FIG. 1, all the n-channel field-effect transistors N₁₃,N₁₄, N₁₅, N₁₆ and N₁₇ forming part of the decoder unit D₂ are turned on and all the associated p-channel field-effect transistors P₁₃, P₁₄, P₁₅, P₁₆ and P₁₇ of the decoder unit D₂ remain in non-conduction states. Under this condition, the decoder unit D₂ produces a logic "1" bit at the output terminal of the inverter I₂ as the output signal bit O₂ of the decoder unit D₂.

The known address decoder circuit thus constructed is directly responsive to the original input address signals, each of which consists of six bits yields a maximum of 2⁶ =64 different combinations or sequences of bits. In comparison with such a large number of possible decoder outputs, the decoder circuit actually has only twelve outputs and, as a corollary of this, necessitates a disproportionately large number of active devices or transistors. As a matter of fact, the decoder unit D₀ which uses all the supplied address bits A₀, A₁, A₂, . . . A₅ available is composed of a total of twelve transistors which consist of the three series connected n-channel field-effect transistors N₀₁ to N₀₆ and the three parallel connected p-channel field-effect transistors N₀₁ to N₀₆ and P₀₁ to P₀₆. Even each of the decoder units D₁₀ and D₁₁ (as well the decoder units D₅ and D₆ not shown) which uses the minimum number of input address bits is composed of a total of six field-effect transistors N₂₂ to N₂₄ and P₂₂ to P₂₄ or N₂₅ to N₂₇ and P₂₅ to P₂₇. Such a large number of field-effect transistors used in the decoder circuit inevitably results in correspondingly large amounts of capacitances provided by the source and drain diffusion regions of the transistors and accordingly in reduction in the switching speed achievable of the decoder circuit. This drawback of a known address decoder circuit is pronounced in a static decoder circuit implemented by full CMOS configuration as in the case of the prior-art decoder circuit shown in FIG. 1.

Whichever of NAND-based logics or NOR-based logics may be adopted in such a full CMOS address decoder circuit, either the n-channel field-effect transistors or the p-channel field-effect transistors implementing the decoder circuit must be connected in series. The larger the number of the series connected field-effect transistors, the lower the performance efficiencies of the individual transistors and accordingly the lower the switching speed of the entire decoder circuit.

Thus, an address decoder circuit of the type shown in FIG. 1 sometimes uses a predecode scheme for the purpose of reducing the number of the transistors to be used in the decoder circuit and thereby increasing the switching speed achievable of the circuit. FIG. 3 of the drawings shows a preferred example of an address decoder circuit which implements such a predecode scheme.

The decoder circuit herein shown is arranged to produce output address bits O₀ to O₁₁ responsive to original input address bits A₀, A₁, A₂, . . . A₅ also in accordance with the schedules represented by the address map of FIGS. 2A or 2B. The decoder circuit is also assumed to comprise a total of twelve decoder units including the shown decoder units D₂, D₁₀ and D₁₁ which are formed by n-channel field-effect transistors N₂₈ to N₃₆ and p-channel field-effect transistors P₂₈ to P₃₆ and which include logic inverters including the inverters I₂, I₁₀ and I₁₁, respectively. The decoder circuit further comprises first, second and third 2-bit predecode circuits PD₁, PD₂ and PD₃ which are directly responsive to the original input signal bits A₀, A₁, A₂, . . . A₅. Each of these 2-bit predecode circuits PD₁, PD₂ and PD₃ is operative to predecode neighboring two bits (A_(2i) and A_(2i+1) where i=0, 1 or 2) of the supplied original input address bits A₀, A₁, A₂, . . . A₅. The first 2-bit predecode circuit PD₁ is responsive to the lower two A₀ and A₁ of the original input address bits A₀, A₁, . . . A₅ to produce four different output bits B₀₀, B₀₁, B₀₂ and B₀₃ respectively representative of the logic ANDs A₀ ·A₁ , A₀ ·A₁, A₀ ·A₁ and A₀ ·A₁ of the input bits A₀ and A₁ and the respective inverted versions thereof. The second 2-bit predecode circuit PD₂ is responsive to the intermediate two A₂ and A₃ of the original input address bits A₀ to A₅ to produce four different output bits B₁₀, B₁₁, B₁₂ and B₁₃ respectively representative of the logic ANDs A₂ ·A₃, A₂ ·A₃, A₂ ·A₃ and A₂ -A₃ of the input bits A₂ and A₃ and the respective inverted versions thereof. The third 2-bit predecode circuit PD₃ is responsive to the intermediate two A₄ and A₅ of the original input address bits A₀ to A₅ to produce four different output bits B₂₀, B₂₁, B₂₂ and B₂₃ respectively representative of the logic ANDs A₄ ·A₅, A₄ ·A₅ and A₄ ·A₅ of the input bits A₄ and A₅ and the respective inverted versions thereof.

When an original input signal A₀ A₁ A₂ A₃ A₄ A₅ in the form of, for example, 00001X is supplied to the decoder circuit thus constructed and arranged, the output bits B₀₂, B₀₃, B₁₀ and B₂₀ respectively representative of the logic ANDs A₀ ·A₁, A₀ ·A₁, A₂ ·A₃ and A₄ ·A₅ of the supplied address bits assume logic "X", "X", "1" and "1" states. Of the field-effect transistors forming part of the decoder unit. D₂, for example, of the circuit shown in FIG. 3, the series connected n-channel field-effect transistors N₃₀ and N₃₁ and one of the parallel connected n-channel field-effect transistors N₂₈ and N₂₉ are thus turned on and the series connected p-channel field-effect transistors P₃₀ and P₃₁ and one of the parallel connected p-channel field-effect transistors P₂₈ and P₂₉ are held in non-conduction states. Under this condition, the decoder unit D₂ produces a logic "1" signal at the output terminal of the inverter I₂ as the output signal bit O₂ of the decoder unit D₂ as in the prior-art address decoder circuit shown in FIG. 1.

In the decoder units D₂ of the circuit shown in FIG. 3, the predecoded signal bits B₀₂ and B₀₃ produced by the first 2-bit predecode circuit PD₁ are supplied to the parallel combination of the n-channel field-effect transistors N₂₈ and N₂₉ of the decoder unit D₂ to produce a logic sum or OR, viz., (A₀ ·A₁ +A₀ ·A₁)=A₁ of the supplied bits. The predecoded signal bits B₀₂ and B₀₃ are also supplied to the series combination of the p-channel field-effect transistors P₂₈ and P₂₉ of the decoder unit D₂ to produce a logic OR, viz., (A₀ ·A₁) +(A₀ ·A₁) =A₁ of the supplied bits. Likewise, the predecoded signal bits B₁₀ and B₁₂ produced by the second 2-bit predecode circuit PD₂ are supplied to the parallel connected n-channel field-effect transistors N₃₂ and N₃₃ and series connected p-channel field-effect transistors P₃₂ and P₃₃ of the decoder unit D₁₀ to produce a logic OR, viz., (A₂ ·A₃ +A₂ ·A₃) =A₂ and a logic OR, viz., (A₂ ·A₃)-+(A₂ ·A₃) =A₂ of the supplied bits. In the decoder unit D₁₁, furthermore, a logic OR, viz., (A₂ ·A₃ +A₂ ·A₃) =A₂ is produced in response to the predecoded signal bits B₁₀ and B₁₂ produced by the second 2-bit predecode circuit PD₂.

In the decoder circuit shown in FIG. 3, the neighboring two A_(2i) and A_(2i) of the supplied original input address bits A₀, A₁, A₂, . . . A₅ are thus predecoded by each of the of 2-bit predecode circuits PD₁, PD₂ and PD₃ into signal bits B₀₀ to B₂₃ each of which is provided by the logic AND of the supplied address bit A_(2i) or the inverted version thereof and the supplied address bit A_(2i+l) or the inverted version thereof. The predecoded signal bits B₀₀ to B₂₃ are used in the decoder units D₂, D₃, D₄, D₅, D₆, D₇, D₁₀ and D₁₁ so that only one of the two original input address bits such as, for example, the address bit A₁ for the decoder unit D₂ or the address bit A₂ for the decoder unit D₁₀ or D₁₁ is effective in the particular decoder unit. This means that the other of the two bits A_(2i) and A_(2i) is virtually neglected from use. Such a scheme of the decoder circuit results in irregularities in the geometrical topology of the decoder circuit fabricated on a semiconductor chip because of the fact that the individual decoder units D₀, D₁, D₂, . . . D₁₁ each of which should be configured by active devices and interconnections patterned with irregularity will differ in topology from one circuit to another.

The present invention contemplates elimination of such a problem inherent in a two-bit predecode decoder circuit of the described nature. Accordingly, the goal of the present invention is to provide an improved decoder circuit which is composed of a minimized number of active devices to achieve an increased switching speed of the decoder circuit and which effectively uses the original input address bits supplied to the decoder circuit, as previously noted.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 4 of the drawings shows the logical configuration of a preferred embodiment of a decoder circuit according to the present invention. The decoder circuit herein shown is also assumed to be designed for use with a 12-word ROM device (not shown) by way of example and thus comprises twelve decoder units D₀, D₁, D₂, . . . D₁₁. The decoder units D₀, D₁, D₂, . . . D₁₁ in turn comprise two-input and three-input logic NAND gates G₀, G₁, G₂, . . . G₁₁, respectively, and logic inverters I₀, I₁, I₂, . . . I₁₁ respectively connected to the output terminals of the NAND gates G₀, G₁, G₂, . . . G₁₁ to provide output address bits of the individual decoder units D₀ to D₁₁.

The decoder circuit embodying the present invention further comprises first, second and third 2-bit predecode circuits PD₁, PD₂ and PD₃ which are directly responsive to original input signal bits A₀, A₁, A₂, . . . A₅ and the inverted versions A₀, A₁, A₂, . . . A₅, respectively, thereof. Each of these 2-bit predecode circuits PD₁, PD₂ and PD₃ is operative to predecode neighboring two bits A_(2i) and A_(2i) +l of the supplied original input address bits A₀, A₁, A₂, . . . A₅ similarly to their counterparts in the decoder circuit described with reference to FIG. 3. Thus, the first 2-bit predecode circuit PD₁ is responsive to the lower two A₀ and A₁ of the original input address bits A₀, A₁, . . . A₅ to produce four different output bits B₀₀, B₀₁ , B₀₂ and B₀₃ respectively representative of the logic ANDs A₀ ·A₁, A₀ ·A₁, A₀ ·A₁, A₀ ·A₁ and A₀ ·A₁ of the input address bits A₀ and A₁ and the respective inverted versions thereof. The second 2-bit predecode circuit PD₂ is responsive to the intermediate two A₂ and A₃ of the original input address bits A₀ to A₅ to produce four different output bits B₁₀, B₁₁, B₁₂ and B₁₃ respectively representative of the logic ANDs A₂ ·A₃, A₂ ·A₃, A₂ ·A₃ and A₂ ·A₃ of the input address bits A₂ and A₃ and the respective inverted versions thereof. The third 2-bit predecode circuit PD₃ is responsive to the intermediate two A₄ and A₅ of the original input address bits A₀ to A₅ to produce four different output bits B₂₀, B₂₁, B₂₂ and B₂₃ respectively representative of the logic ANDs A₄ ·A₅, A₄ ·A₅, A₅ ·A₅ and A₄ ·A₅ of the input address bits A₄ and A₅ and the respective inverted versions thereof. The decoder circuit thus comprising the twelve NAND gates G₀ to G₁₁ are responsive to the original input address bits A₀ to A₅ and the respective inverted versions of these bits and to the signal bits B₀₀ to B₂₃ through a total of twelve input lines as shown. The individual decoder units D₀ to D₁₁ are implemented by full CMOS configuration and are operative to produce output address bits O₁ to O₁₁ in response to the supplied address bits A₀ to A₅ and A₀ to A₅ basically also in accordance with the schedules represented by the address maps depicted in FIGS. 2A and 2B.

FIG. 5 shows an example of the transistor circuit arrangement implementing the logical configuration of the decoder circuit thus constructed.

As shown, the three-input NAND gate G₀ of the decoder unit D₀ comprises three n-channel field-effect transistors N₄₀, N₄₁ and N₄₂ connected in series between the logic inverter I₀ and ground and three p-channel field-effect transistors P₄₀, P₄₁ and P₄₂ connected in parallel between the logic inverter I₀ and a source of a supply voltage V_(CC). The field-effect transistors N₄₀ and P₄₀ have their gates responsive to the predecoded signal bit B₀₀, the field-effect transistors N₄₁ and P₄₁ have their gates responsive to the preselected signal bit B₁₀, and the field-effect transistors N₄₂ and P₄₃ have their gates responsive to the predecoded signal bit B₂₀.

The three-input NAND gate G₁ of the decoder unit D₁ comprises three n-channel field-effect transistors N₄₃, N₄₄ and N₄₅ connected in series between the logic inverter I₁ and ground and three p-channel field-effect transistors P₄₃, P₄₄ and P₄₅ connected in parallel between the logic inverter I₁ and the source of the supply voltage V_(CC). The field-effect transistors N₄₃ and P₄₃ have their gates responsive to the predecoded signal bit B₀₁, the field-effect transistors N₄₄ and P₄₄ have their gates responsive to the predecoded signal bit B₁₀, and the field-effect transistors N₄₅ and P₄₅ have their gates responsive to the predecoded signal bit B₂₀.

The three-input NAND gate G₂ of the decoder unit D₂ comprises three n-channel field-effect transistors N₄₆, N₄₇ and N₄₈ connected in series between the logic inverter I₂ and ground and three p-channel field-effect transistors P₄₆, P₄₇ and P₄₈ connected in parallel between the logic inverter I₂ and the source of the supply voltage V_(CC). The field-effect transistors N₄₆ and P₄₆ have their gates responsive to the predecoded signal bit B₁₀, the field-effect transistors N₄₇ and P₄₇ have their gates responsive to the predecoded signal bit B₂₀, and the field-effect transistors N₄₈ and P₄₈ have their gates responsive to the original input address bit A₁.

The two-bit NAND gate G₃ of the decoder unit D₃ comprises two n-channel field-effect transistors N₄₉ and N₅₀ connected in series between the logic inverter I₃ and ground and two p-channel field-effect transistors P₄₉ and P₅₀ connected in parallel between the logic inverter I₃ and the source of the supply voltage V_(CC). The field-effect transistors N₄₉ and P₄₉ have their gates responsive to the predecoded signal bit B₁₁ and the field-effect transistors N₅₀ and P₅₀ have their gates responsive to the predecoded signal bit B₂₀.

As will be seen from FIG. 4, each of the two-input NAND gates G₄, G₅ and G₆ of the decoder units D₄, D₅ and D₆, respectively, comprises two n-channel field-effect transistors connected in series between each of the logic inverters I₄, I₅ and I₆ and ground and two p-channel field-effect transistors connected in parallel between each of the logic inverters I₄, I₅ and I₆ and the source of the supply voltage V_(CC). One pair of n-channel and p-channel field-effect transistors of the NAND gate G₄ have their responsive to the predecoded signal bit B₂₀ and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G₄ have their gates responsive to the original input address bit A₃. One pair of n-channel and p-channel field-effect transistors of the NAND gate G₅ have their gates responsive to the predecoded signal bit B₂₁ and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G₅ have their gates also responsive to the original input address bit A₃. Furthermore, one pair of n-channel and p-channel field-effect transistors of the NAND gate G₆ have their gates responsive to the predecoded signal bit B₁₀ and the other pair of n-channel and p-channel field-effect transistors of the NAND gate G₅ have their gates responsive to the predecoded signal bit B₂₂.

As will be further seen from FIG. 4, each of the three-input NAND gates G₇, G₈ and G₉ of the decoder units D₇, D₈ and D₉, respectively, comprises three n-channel field-effect transistors connected in series between each of the logic inverters I₇, I₈ and I₉ and ground and two p-channel field-effect transistors connected in parallel between each of the logic inverters I₇, I₈ and I₉ and the source of the supply voltage V_(CC). One pair of n-channel and p-channel field-effect transistors of the NAND gate G₇ have their gates responsive to the predecoded signal bit B₁₁, another pair of n-channel and p-channel field-effect transistors of the NAND gate G₇ have their gates responsive to the predecoded signal bit B₂₂, and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G₇ have their gates responsive to the inverted address bit A₁. One pair of n-channel and p-channel field-effect transistors of the NAND gate G₈ have their gates responsive to the predecoded signal bit B₀₂, another pair of n-channel and p-channel field-effect transistors of the NAND gate G₈ have their gates responsive to the predecoded signal bit B₁₁, and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G₈ have their gates responsive to the predecoded signal bit B₂₂. Furthermore, one pair of n-channel and p-channel field-effect transistors of the NAND gate G₉ have their gates responsive to the predecoded signal bit B₀₃, another pair of n-channel and p-channel field-effect transistors of the NAND gate G₉ have their gates responsive to the predecoded signal bit B₁₁, and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G₉ have their gates responsive to the predecoded signal bit B₁₁, and the remaining pair of n-channel and p-channel field-effect transistors of the NAND gate G₈ have their gates responsive to the predecoded signal bit B₂₂.

As shown in FIG. 5, the two-input NAND gate G₁₀ of the decoder unit D₁₀ comprises two n-channel field-effect transistors N₅₁ and N₅₂ connected in series between the logic inverter I₁₀ and ground and two p-channel field-effect transistors P₅₁ and P₅₂ connected in parallel between the logic inverter I₁₀ and the source of the supply voltage V_(CC). The field-effect transistors N₅₁ and P₅₁ have their gates responsive to the predecoded signal bit B₂₃ and the field-effect transistors N₅₂ and P₅₂ have their gates responsive to the inverted address bit A₂. Lastly, the two-input NAND gate G₁₁ of the decoder unit D₁₁ comprises two n-channel field-effect transistors N₅₃ and N₅₄ connected in series between the logic inverter I₁₁ and ground and two p-channel field-effect transistors P₅₃ and P₅₄ connected in parallel between the logic inverter I₁₁ and the source of the supply voltage V_(CC). The field-effect transistors N₅₃ and P₅₃ have their gates also responsive to the predecoded signal bit B₂₃ and the field-effect transistors N₅₄ and P₅₄ have their gates responsive to the original input address bit A₂ as shown.

It may be herein noted that FIG. 5 herein presented shows not only the general circuit arrangement or interconnections between the individual transistors used but also a preferred example of the layout of the transistors arranged in rows and columns on a semiconductor integrated circuit chip in conjunction with the terminals providing the supply voltage source and ground lines.

The active devices of the decoder circuit being thus arranged, the respective NAND gates G₀ to G₁₁ of the decoder units D₀ to D₁₁ are operative to produce output bits O₀ to O₁₁ in accordance with the schemes represented by the following Boolean expressions:

O₀ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₁ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₂ =A₁ ·(A₂ ·A₃)·(A₄ ·A₅)=A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₃ =(A₂ ·A₃)·(A₄ ·A₅)=A₂ ·A₃ ·A₄ ·A₅

O₄ =A₃ ·(A₄ ·A₅)=A₃ ·A₄ ·A₅

O₅ =A₃ ·(A₄ ·A₅)=A₃ ·A₄ ·A₅

O₆ =(A₂ ·A₃)·(A₄ ·A₅)=A₂ ·A₃ ·A₄ ·A₅

O₇ =A₁ ·(A₂ ·A₃)·(A₄ ·A₅)=A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₈ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₉ =(A₀ ·A₁)·(A₂ ·A₃)·(A₄ ·A₅)=A₀ ·A₁ ·A₂ ·A₃ ·A₄ ·A₅

O₁₀ =A₂ ·(A₄ ·A₅)=A₂ ·A₄ ·A₅

O₁₁ =A₂ ·(A₄ ·A₅)=A₂ ·A₄ ·A₅

As will be seen from the address maps of FIGS. 2A and 2B, the address bits O₀ to O₁₁ produced by the individual decoder units D₀ to D₁₁ , viz., appearing at the output terminals of the logic inverters I₀ to I₁₁, respectively, assume logic "0" values as follows:

The output address bit O₀ assumes a logic "0" value when all of the original input address bits A₀ to A₅ are of logic "0". The output address bit O₁ assumes a logic "0" value when the original input address bit A₀ is of a logic "1" value and each of the remaining original input address bits A₁ to A₅ is of a logic "0" value. The output address bit O₂ assumes a logic "0" value without respect to the original input address bit A₀ when the original input address bit A₁ is of a logic "1" value and each of the remaining original input address bits A₂ to A₅ is of a logic "0" value. The output address bit O₃ assumes a logic "0" value without respect to the original input address bits A₀ and A₁ when the original input address bit A₂ is of a logic "1" value and each of the remaining original input address bits A₃ to A₅ is of a logic "0" value. The output address bit O₄ assumes a logic "0" value without respect to the original input address bits A₀ to A₂ when the original input address bit A₃ is of a logic "1" value and each of the remaining original input address bits A₄ and A₅ is of a logic "0" value. The output address bit O₅ assumes a logic "0" value without respect to the original input address bits A₀ to A₂ when each of the original input address bits A₃ and A₄ is of a logic "1" value and the remaining original input address bit A₅ is of a logic "0" value. The output address bit O₆ assumes a logic "0" value without respect to the original input address bits A₀ and A₁ when each of the original input address bits A₂ to A₄ is of a logic "0" value and the remaining original input address bit A₅ is of a logic "1" value. The output address bit O₇ assumes a logic "0" value without respect to the original input address bit A₀ when the original input address bits A₁, A₃ and A₄ is of a logic "0" value and each of the remaining original input address bits A₂ and A₅ is of a logic "1" value. The output address bit O₈ assumes a logic "0" value when each of the original input address bits A₀, A₃ and A₄ is of a logic "0" value and each of the remaining original input address bits A₁, A₂ and A₅ is of a logic "1" value. The output address bit O₉ assumes a logic "0" value when each of the original input address bits A₀, A₁, A₂ and A₅ is of a logic "1" value and each of the remaining original input address bits A₃ and A₅ is of a logic "0" value. The output address bit O₁₀ assumes a logic "0" value without respect to the original input address bits A₀, A₁ and A₃ when the original input address bit A₂ is of a logic "0" value and each of the remaining original input address bits A₄ and A₅ is of a logic "1" value. The output address bit O₁₁ assumes a logic "0" value without respect to the original input address bits A₀, A₁ and A₃ when all the remaining input address bits A₂, A₄ and A₅ are of logic "1" values.

Thus, each of the decoder units D₀, D₁, D₈ and D₉ is responsive to all of the six supplied original input address bits A₀ to A₅. Accordingly, each of these decoder units D₀, D₁, D₈ and D₉ is responsive to a single unique sequence or combination of the input address bits and is accordingly comprised of a three-input NAND gate responsive to three of the predecoded signal bits alone. Each of the decoder units D₂ and D₇ is not responsive to one of the supplied original input address bits A₀ to A₅ and is thus responsive to two different sequences or combinations of the input address bits. Each of these two decoder units D₂ and D₇ may therefore be comprised of a three-input NAND gate responsive to two of the predecoded signal bits and one of the original input address bits. Each of the decoder units D₃ and D₆ is not responsive to two of the supplied original input address bits A₀ to A₅ and is thus responsive to four different sequences or combinations of the input address bits and may therefore be comprised of a two-input NAND gate for being responsive to two of the predecoded signal bits alone. Each of the decoder units D₄, D₅, D₁₀ and D₁₁ is not responsive to three of the supplied original input address bits A₀ to A₅ and is responsive to eight different sequences or combinations of the input address bits. Each of these decoder units D₄, D₅, D₁₀ and D₁₁ may therefore be also comprised of a two-input NAND gate for being responsive to one of the predecoded signal bits and one of the original input address bits.

From the above discussion it will have been understood that the decoder units D₀ to D₁₁ of the decoder circuit embodying the present invention are broken down to four different categories which consist of a first category including the decoder units D₀, D₂, D₈ and D₉ each including a three-input NAND gate responsive to predecoded signal bits alone, a second category including the decoder units D₃ and D₆ each including a two-input NAND gate also responsive to predecoded signal bits alone, a third category including the decoder units D₂ and D₇ each including a three-input NAND gate responsive to predecoded signal bits and an original input address bit, and a fourth category including the decoder units D₄, D₅, D₁₀ and D₁₁ each including a two-input NAND gate responsive to a predecoded signal bit and an original input address bit. In each of the decoder units D₂ and D₇ which fall within the third category, the original input address bit used directly by the decoder unit is selected from the bits other than those which have resulted in the two predecoded signal bits used by the decoder unit. In each of the decoder units D₄, D₅, D₁₀ and D₁₁ which fall within the fourth category, the original input address bit used is also selected from the bits other than those which have resulted in the single predecoded signal bit used by the decoder unit.

As will have been seen from the foregoing description, the decoder circuit embodying the present invention is characterized in that, inter alia, the predecoded signal bits are used in combination with the original input address bits in most of the decoder units such as the decoder units D₂, D₄, D₅, D₇ , D₁₀ and D₁₁. For this reason, each of the decoder units D₀ to D₁₁ of the decoder circuit embodying the present invention can be implemented by a two-input or three-input NAND gate and can accordingly be composed of only two or three CMOS transistor parts in addition to the associated logic converter. Such a configuration of the decoder circuit embodying the present invention is prominently contrasted by a prior-art address decoder circuit which includes more than three CMOS transistor pairs as described with reference to FIG. 1. A decoder circuit according to the present invention is thus advantageous for its simplicity of construction and accordingly for the reduced switching time achievable of the decoder circuit over a prior-art decoder circuit of the described nature. The reduction in the number of series connected n-channel field-effect transistors of each of the decoder units significantly contributes to reduction in the transconductance (gm) of the decoder unit as a whole and will make it possible further reduce the switching time of the decoder circuit.

While the predecode circuits used in the described embodiment of a decoder circuit have been assumed to be of the two-bit predecode type, any other types of predecode circuits such as six-bit or three-bit predecode circuits may alternatively be used in a decoder circuit according to the present invention.

Furthermore, all of the input lines for the original input address bits and the inverted versions thereof have been shown connected to the decoder circuit but, if desired, only those for the original input address bits A₁, A₂ and A₃ and the inverted version A₂ of the original input address bit A₂ which are used directly by the decoder circuit may be connected to the decoder circuit. In this instance, the other input lines may be connected only to the predecode circuit PD₁, PD₂ and PD₃ without being extended far to the decoder units per se. 

What is claimed is:
 1. A decoder circuit for decoding different combinations of supplied original input signals on input signal lines, comprising at least one predecode circuit coupled to said input signal lines for producing predecoded output signals on output lines of said predecode circuit, and a plurality of decoder units including .[.at least one decoder unit coupled to at least two different combinations of said input signal lines, and.]. at least one decoder unit coupled to the combination of at least one of said output lines and at least one of said input signal lines.
 2. A decoder circuit for decoding different combinations of supplied original input signals on input signal lines, comprising at least one predecode circuit coupled to said input signal lines for producing predecoded output signals on output lines of said predecode circuit, and a plurality of decoder units including .[.at least one decoder unit coupled to at least two different combinations of said input signal lines,.]. at least one decoder unit coupled to selected ones of said output signal lines alone and a decoder unit coupled to at least one of said output signal lines and at least one of said input signal lines.
 3. A decoder circuit as set forth in claim 1 or 2, in which each of said plurality of decoder units comprises a logic NAND gate.
 4. A semiconductor decoder circuit including a plurality of decoder units for decoding different combinations of supplied original input signals on input signal lines, comprising:a first set of signal lines formed on a semiconductor structure, the first set of signal lines comprising a first group of signal lines connected to a source of a first predetermined voltage and a second group of signal lines connected to a source of a second predetermined voltage, a second set of signal lines formed on a semiconductor structure and extending substantially at right angles to said first set of signal lines, the second set of signal lines comprising a third group of signal lines respectively coupled to output signal lines having output signals predecoded from the input signals on selected ones of said input signal lines and a fourth group of signal lines respectively coupled to the input signals on selected ones of said input signal lines, a first set of field-effect transistors selectively connected in series to the source of said first predetermined voltage along each of the signal lines of said first predetermined voltage along each of the signal lines of said first group, each of the first set of field-effect transistors being of one channel conductivity type, and a second set of field-effect transistors selectively connected in parallel to the source of said second predetermined voltage along each of the signal lines of said second group, each of the second set of field-effect transistors being of the channel conductivity type opposite to said one channel conductivity type, the second set of field-effect transistors having their gates selectively connected to the signal lines of said third and fourth groups, the first set of field-effect transistors arranged along each of the signal lines of said first group and the second set of field-effect transistors arranged along each of the signal lines of said second group implementing each of said decoder units. 